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rev. 1.2 12/09 copyright ? 2009 by silicon labora tories si8410/20/21 si8410/20/21 iso pro l ow -p ower s ingle and d ual -c hannel d igital i solators features applications safety regulatory approvals description the silicon laboratories? family of ultra low power digital isolators are cmos devices that employ an rf coup ler to transmit digital information across an isolation barrier. very high speed operation at low power levels is achieved. these devices are ava ilable in an 8-pin narrow-body soic package. two speed grade options (1 and 150 mbps) are available and achieve worst-case propagation delays of less than 10 ns. block diagram ? high-speed operation ?? dc to 150 mbps ? low propagation delay ?? <10 ns worst case ? wide operating supply voltage: 2.70?5.5 v ? ultra low power (typical) 5 v operation: ?? < 2.1 ma per channel at 1 mbps ?? < 2.4 ma per channel at 10 mbps ?? < 6 ma per channel at 100 mbps 2.70 v operation: ?? < 1.8 ma per channel at 1 mbps ?? < 2.1 ma per channel at 10 mbps ?? < 4 ma per channel at 100 mbps ? precise timing (typical) ?? 1.5 ns pulse width distortion ?? 0.5 ns channel-channel skew ?? 2 ns propagation delay skew ? up to 2500 v rms isolation ? transient immunity ?? 25 kv/s ? dc correct ? no start-up init ialization required ? 15 s startup time ? high temperature operation ?? 125 c at 150 mbps ? narrow body soic-8 package ? rohs compliant ? isolated switch mode supplies ? isolated adc, dac ? motor control ? power factor correction systems ? ul 1577 recognized ?? 2500 v rms for 1 minute ? csa component notice 5a approval ?? iec 60950, 61010 approved ? vde certification conformity ?? iec 60747-5-2 (vde0884 part 2) si8420 si8421 a1 b1 si8410 a2 a1 b2 b1 a2 a1 b2 b1 patents pending pin assignments narrow body soic v dd1 a1 gnd1 1 2 3 4 5 6 7 8 top view v dd2 b1 gnd2 a2 b2 v dd1 a1 gnd1 1 2 3 4 5 6 7 8 top view v dd2 gnd2 b1 gnd2 v dd1 si841x si842x
si8410/20/21 2 rev. 1.2
si8410/20/21 rev. 1.2 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2. eye diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 3.3. layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4. errata and design migration guid elines (revision c only) . . . . . . . . . . . . . . . . . . . . . . 22 4.1. power supply bypass capacitors (revision c only) . . . . . . . . . . . . . . . . . . . . . . . .22 4.2. latch up immunity (rev ision c only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7. package outline: 8-pin narrow body so ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 8. landing pattern: 8-pin narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
si8410/20/21 4 rev. 1.2 1. electrical specifications table 1. electrical characteristics (v dd1 = 5 v 10%, v dd2 = 5 v 10%, t a =?40 to 125oc) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 4.8 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 1 z o ?8 5? ? dc supply current (all inputs 0 v or at supply) si8410ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 0.8 0.8 1.8 0.8 1.2 1.2 2.7 1.2 ma si8420ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.0 1.3 3.0 1.4 1.5 2.0 4.5 2.1 ma si8421ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.3 1.3 2.3 2.3 2.0 2.0 3.5 3.5 ma 1 mbps supply current (all inputs = 500 khz square wa ve, ci = 15 pf on all outputs) si8410ax, bx v dd1 v dd2 ? ? 1.3 0.9 2.0 1.4 ma si8420ax, bx v dd1 v dd2 ? ? 2.0 1.6 3.0 2.4 ma si8421ax, bx v dd1 v dd2 ? ? 1.9 1.9 2.9 2.9 ma notes: 1. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
si8410/20/21 rev. 1.2 5 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 1.3 1.2 2.0 1.8 ma si8420bx v dd1 v dd2 ? ? 2.0 2.1 3.0 3.2 ma si8421bx v dd1 v dd2 ? ? 2.2 2.2 3.3 3.3 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 1.4 4.6 2.1 5.8 ma si8420bx v dd1 v dd2 ? ? 2.2 9.2 3.3 11.5 ma si8421bx v dd1 v dd2 ? ? 5.8 5.8 7.3 7.3 ma table 1. electrical characteristics (continued) (v dd1 = 5 v 10%, v dd2 = 5 v 10%, t a =?40 to 125oc) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output.
si8410/20/21 6 rev. 1.2 figure 1. propagation delay timing timing characteristics si8410ax, si8420ax, si8421ax maximum data rate 0 ? 1.0 mbps minimum pulse width ? ? 250 ns propagation delay t phl , t plh see figure 1 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 1 ? ? 25 ns propagation delay skew 2 t psk(p-p) ? ? 40 ns channel-channel skew t psk ? ? 35 ns si8410bx, si8420bx, si8421bx maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.0 ns propagation delay t phl , t plh see figure 1 3.0 6.0 9.5 ns pulse width distortion |t plh - t phl | pwd see figure 1 ? 1.5 2.5 ns propagation delay skew 2 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 8n s all models output rise time t r c l = 15 pf ? 3.8 5.0 ns output fall time t f c l = 15 pf ? 2.8 3.7 ns common mode transient immunity cmti v i =v dd or 0 v ? 25 ? kv/s start-up time 3 t su ?1 54 0 s table 1. electrical characteristics (continued) (v dd1 = 5 v 10%, v dd2 = 5 v 10%, t a =?40 to 125oc) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pi ns should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature. 3. start-up time is the time period from the applic ation of power to valid data at the output. typical input t plh t phl typical output t r t f 90% 10% 90% 10% 1.4 v 1.4 v
si8410/20/21 rev. 1.2 7 table 2. electrical characteristics (v dd1 = 3.3 v 10%, v dd2 = 3.3 v 10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 3.1 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 1 z o ?8 5? ? dc supply current (all inputs 0 v or at supply) si8410ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 0.8 0.8 1.8 0.8 1.2 1.2 2.7 1.2 ma si8420ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.0 1.3 3.0 1.4 1.5 2.0 4.5 2.1 ma si8421ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.3 1.3 2.3 2.3 2.0 2.0 3.5 3.5 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8410ax, bx v dd1 v dd2 ? ? 1.3 0.9 2.0 1.4 ma si8420ax, bx v dd1 v dd2 ? ? 2.0 1.6 3.0 2.4 ma si8421ax, bx v dd1 v dd2 ? ? 1.9 1.9 2.9 2.9 ma notes: 1. the nominal output impedance of an isol ator driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. start-up time is the time period from the a pplication of power to valid data at the output.
si8410/20/21 8 rev. 1.2 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 1.3 1.2 2.0 1.8 ma si8420bx v dd1 v dd2 ? ? 2.0 2.1 3.0 3.2 ma si8421bx v dd1 v dd2 ? ? 2.2 2.2 3.3 3.3 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 1.3 3.3 2.0 4.9 ma si8420bx v dd1 v dd2 ? ? 2.0 6.5 3.0 8.1 ma si8421bx v dd1 v dd2 ? ? 4.4 4.4 5.5 5.5 ma timing characteristics si8410ax, si8420ax, si8421ax maximum data rate 0?1.0mbps minimum pulse width ??250ns propagation delay t phl , t plh see figure 1 ? ? 35 ns pulse width distortion |t plh ? t phl | pwd see figure 1 ? ? 25 ns propagation delay skew 2 t psk(p-p) ? ? 40 ns channel-channel skew t psk ? ? 35 ns table 2. electrical characteristics (continued) (v dd1 = 3.3 v 10%, v dd2 = 3.3 v 10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isol ator driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. start-up time is the time period from the a pplication of power to valid data at the output.
si8410/20/21 rev. 1.2 9 si8410bx, si8420bx, si8421bx maximum data rate 0?150mbps minimum pulse width ??6.0ns propagation delay t phl , t plh see figure 1 3.0 6.0 9.5 ns pulse width distortion |t plh ? t phl | pwd see figure 1 ? 1.5 2.5 ns propagation delay skew 2 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 8n s all models output rise time t r c l = 15 pf ? 4.3 6.1 ns output fall time t f c l = 15 pf ? 3.0 4.3 ns common mode transient immunity cmti v i =v dd or 0 v ? 25 ? kv/s start-up time 3 t su ?1 54 0 s table 2. electrical characteristics (continued) (v dd1 = 3.3 v 10%, v dd2 = 3.3 v 10%, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. the nominal output impedance of an isol ator driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driv er fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, l oad, and ambient temperature. 3. start-up time is the time period from the a pplication of power to valid data at the output.
si8410/20/21 10 rev. 1.2 table 3. electrical characteristics 1 (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 c) parameter symbol test condition min typ max unit high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma v dd1 ,v dd2 ?0.4 2.3 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 2 z o ?8 5? ? dc supply current (all inputs 0 v or at supply) si8410ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 0.8 0.8 1.8 0.8 1.2 1.2 2.7 1.2 ma si8420ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.0 1.3 3.0 1.4 1.5 2.0 4.5 2.1 ma si8421ax, bx v dd1 v dd2 v dd1 v dd2 all inputs 0 dc all inputs 0 dc all inputs 1 dc all inputs 1 dc ? ? ? ? 1.3 1.3 2.3 2.3 2.0 2.0 3.5 3.5 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8410ax, bx v dd1 v dd2 ? ? 1.3 0.9 2.0 1.4 ma si8420ax, bx v dd1 v dd2 ? ? 2.0 1.6 3.0 2.4 ma si8421ax, bx v dd1 v dd2 ? ? 1.9 1.9 2.9 2.9 ma notes: 1. specifications in this table are also valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. start-up time is the time period from the a pplication of power to valid data at the output.
si8410/20/21 rev. 1.2 11 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 1.3 1.2 2.0 1.8 ma si8420bx v dd1 v dd2 ? ? 2.0 2.1 3.0 3.2 ma si8421bx v dd1 v dd2 ? ? 2.2 2.2 3.3 3.3 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8410bx v dd1 v dd2 ? ? 1.3 2.7 2.0 4.0 ma si8420bx v dd1 v dd2 ? ? 2.0 5.2 3.0 6.5 ma si8421bx v dd1 v dd2 ? ? 3.7 3.7 4.6 4.6 ma timing characteristics si8410ax, si8420ax, si8421ax maximum data rate 0 ? 1.0 mbps minimum pulse width ? ? 250 ns propagation delay t phl , t plh see figure 1 ? ? 35 ns pulse width distortion |t plh - t phl | pwd see figure 1 ? ? 25 ns propagation delay skew 3 t psk(p-p) ? ? 40 ns channel-channel skew t psk ? ? 35 ns table 3. electrical characteristics 1 (continued) (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. specifications in this table are also valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. start-up time is the time period from the a pplication of power to valid data at the output.
si8410/20/21 12 rev. 1.2 si8410bx, si8420bx, si8421bx maximum data rate 0 ? 150 mbps minimum pulse width ? ? 6.0 ns propagation delay t phl , t plh see figure 1 3.0 6.0 9.5 ns pulse width distortion |t plh - t phl | pwd see figure 1 ? 1.5 2.5 ns propagation delay skew 3 t psk(p-p) ?2 . 03 . 0n s channel-channel skew t psk ?0 . 51 . 8n s all models output rise time t r c l = 15 pf ? 4.8 6.5 ns output fall time t f c l = 15 pf ? 3.2 4.6 ns common mode transient immunity cmti v i =v dd or 0 v ? 25 ? kv/s start-up time 4 t su ?1 54 0 s table 3. electrical characteristics 1 (continued) (v dd1 = 2.70 v, v dd2 = 2.70 v, t a = ?40 to 125 c) parameter symbol test condition min typ max unit notes: 1. specifications in this table are also valid at vdd1 = 2.6 v and vdd2 = 2.6 v when the operating temperature range is constrained to t a = 0 to 85 c. 2. the nominal output impedance of an isolat or driver channel is approximately 85 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation de lay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. start-up time is the time period from the a pplication of power to valid data at the output.
si8410/20/21 rev. 1.2 13 table 4. absolute maximum ratings 1 parameter symbol min typ max unit storage temperature 2 t stg ?65 ? 150 c operating temperature t a ?40 ? 125 c supply voltage (revision c) 3 v dd1 , v dd2 ?0.5 ? 5.75 v supply voltage (revision d) 3 v dd1 , v dd2 ?0.5 ? 6.0 v input voltage v i ?0.5 ? v dd + 0.5 v output voltage v o ?0.5 ? v dd + 0.5 v output current drive channel i o ??10ma lead solder temperature (10 s) ? ? 260 c maximum isolation voltage (1 s) ? ? 3600 v rms notes: 1. permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. vde certifies storage temper ature from ?40 to 150 c. 3. see "6. ordering guide" on page 24 for more information. table 5. recommended operating conditions parameter symbol test condition min typ max unit ambient operating temperature* t a 150 mbps, 15 pf, 5 v ?40 25 125 c supply voltage v dd1 2.70 ? 5.5 v v dd2 2.70 ? 5.5 v *note: the maximum ambient temperature is dependent upon data frequency, output loading, the number of operating channels, and supply voltage. table 6. regulatory information* csa the si84xx is certified under csa component acceptan ce notice 5a. for more details, see file 232873. vde the si84xx is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. ul the si84xx is certified under ul1577 component recognition program. for more details, see file e257455. *note: regulatory certifications apply to 2.5 kv rms rated devices which are production tested to 3.0 kv rms for 1 sec. for more information, see "6. ordering guide" on page 24.
si8410/20/21 14 rev. 1.2 table 7. insulation and safety-related specifications parameter symbol test condition value unit nominal air gap (clearance) 1 l(io1) 4.9 mm nominal external tracking (creepage) 1 l(io2) 4.01 mm minimum internal gap (internal clearance) 0.008 mm tracking resistance (comparative tracking index) cti din iec 60112/vde 0303 part 1 >175 v resistance (input-output) 2 r io 10 12 ? capacitance (input-output) 2 c io f=1mhz 1.0 pf input capacitance 3 c i 4.0 pf notes: 1. the values in this table correspond to the nominal creepa ge and clearance values as detailed in "7. package outline: 8-pin narrow body soic" on page 25. vde certifies the clearance and creepage limits as 4.7 mm minimum for the nb soic-8 package. ul does not impose a clearance and cree page minimum for component level certifications. csa certifies the clearance and creepage limits as 3.9 mm minimum for the nb soic-8 package. 2. to determine resistance and capacitance, the si84xx is converted into a 2-terminal device. pins 1?4 are shorted together to form the first terminal and pins 5?8 are shorte d together to form the second terminal. the parameters are then measured between these two terminals. 3. measured from input pin to ground. table 8. iec 60664-1 (vde 0844 part 2) ratings parameter test conditions specification basic isolation group material group iiia installation classification rated mains voltages < 150 v rms i-iv rated mains voltages < 300 v rms i-iii rated mains voltages < 400 v rms i-ii
si8410/20/21 rev. 1.2 15 table 9. iec 60747-5-2 insulation characteristics for si84xxxb* parameter symbol test cond ition characteristic unit maximum working insulation voltage v iorm 560 v peak input to output test voltage v pr method a after environmental tests subgroup 1 (v iorm x1.6=v pr , t m =60sec, partial discharge < 5 pc) 896 v peak method b1 (v iorm x 1.875 = v pr , 100% production test, t m =1 sec, partial discharge < 5 pc) 1050 after input and/or safety test subgroup 2/3 (v iorm x1.2=v pr , t m =60sec, partial discharge < 5 pc) 672 highest allowable overvoltage (transient overvoltage, t tr =10 sec) v tr 4000 v peak pollution degree (din vde 0110, table 1) 2 insulation resistance at t s , v io =500v r s >10 9 ? *note: the si84xx is suitable for basic electrical isolation with a climate classification of 40/125/21. table 10. iec safety limiting values 1 parameter symbol test condition min typ max unit case temperature t s ? ? 150 c safety input, output, or supply current i s ? ja = 140 c/w, v i =5.5v, t j =150c, t a =25c ??160ma device power dissipation 2 p d ??150mw notes: 1. maximum value allowed in the event of a failure; also see the thermal derating curve in figure 2. 2. the si841x/2x is tested with vdd1 = vdd2 = 5.5 v, tj = 150 c, cl = 15 pf, input a 150 mbps 50% duty cycle square wave.
si8410/20/21 16 rev. 1.2 figure 2. (nb soic-8) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 11. thermal characteristics parameter symbol test condition min typ max unit ic junction-to-air thermal resistance ? ja ?140?c/w table 12. si84xx logic operation table v i input 1,4 vddi state 1,2,3 vddo state 1,2,3 v o output 1, 4 comments hp p h normal operation. lp p l xup p l upon transition of vddi from unpowered to pow- ered, v o returns to the same state as v i in less than 1 s. x p up undetermined upon transition of vddo from unpowered to pow- ered, v o returns to the same state as v i within 1s. notes: 1. vddi and vddo are the input and output power supplies. v i and v o are the respective input and output terminals. 2. powered (p) state is defined as 2.70 v < vdd < 5.5 v. 3. unpowered (up) state is defined as vdd = 0 v. 4. x = not applicable; h = logic high; l = logic low. 0 200 150 100 50 400 200 100 0 case temperature (oc) safety-limiting values (ma) 320 300 v dd1 , v dd2 = 2.70 v v dd1 , v dd2 = 3.3 v v dd1 , v dd2 = 5.5 v 270 160
si8410/20/21 rev. 1.2 17 2. typical performance characteristics the typical performance characteristics de picted in the following diagrams are for information purposes only. refer to tables 1, 2, and 3 for actual specification limits. figure 3. si8410 typical v dd1 supply current vs. data rate 5, 3.3, and 2.70 v operation figure 4. si8420 typical v dd1 supply current vs. data rate 5, 3.3, and 2.70 v operation figure 5. si8421 typical v dd1 or v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 6. si8410 typical v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 7. si8420 typical v dd2 supply current vs. data rate 5, 3.3, and 2.70 v operation (15 pf load) figure 8. propagation delay vs. temperature 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 0 102030405060708090100110120130140150 data rate (mbps) current (ma) 5v 3.3v 2.70v 0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 data rate (mbps) current (ma) 5v 2.70v 3.3v 5 6 7 8 9 10 -40 -20 0 20 40 60 80 100 120 temperature (degrees c) delay (ns) rising edge falling edge
si8410/20/21 18 rev. 1.2 3. application information 3.1. theory of operation the operation of an si84xx channel is analogous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple archit ecture provides a robust isolated data path and requires no special considerations or initializat ion at start-up. a simplified block diagra m for a single si84xx channel is shown in figure 9. figure 9. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driv er. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consum ption, and better immunity to magnetic fields. see figure 10 for more details. figure 10. modulation scheme rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver input signal output signal modulation signal
si8410/20/21 rev. 1.2 19 3.2. eye diagram figure 11 illustrates an eye-diagram tak en on an si8410 . for the data source, the test used an anritsu (mp1763c) pulse pattern generator set to 1000 ns/div. the output of the generator's clock and data from an si8410 were captured on an oscillosc ope. the results illustra te that data integrity was mainta ined even at the high data rate of 150 mbps. the results also show that 2 ns pulse wid th distortion and 250 ps peak jitter were exhibited. figure 11. eye diagram
si8410/20/21 20 rev. 1.2 3.3. layout recommendations dielectric isolation is a set of specific ations produced by safety regulatory agencies from around the world, which describes the physical construction of electrical equipment that derives power from high-voltage power systems, such as 100?240 v ac systems or industrial power. the dielectr ic test (or hipot test) given in the safety specifications places a very high voltage between the input power pins of a product an d the user circuits and the user-touchable surfaces of the product. for the iec rela ting to products deriving their power from the 100?240 v ac power grids, the minimum test voltage is 2500 v ac (or 3750 v dc , the peak equivalent voltage). there are two terms described in the safety specifications: ? creepage?the distance along the insulating surface an arc may travel. ? clearance?the shortest distance through air that an arc may travel. figure 12 illustrates the accepted me thod of providing the proper creepage distance along the surface.for a 120 v ac application, this distance is 3.2 mm, and the na rrow-body soic package can be used. for a 220?240 v ac application, this distance is 6.4 mm, and a wide-body soic package must be used. there must be no copper traces within this 3.2 or 6.4 mm exclusion area, and the surface should have a conforma l coating, such as solder resist. the digital isolator chip must straddle this exclusion area. figure 12. creepage distance 3.3.1. supply bypass the si841x and si842x fa milies require a 1 f bypass capacitor between v dd1 and gnd1 and v dd2 and gnd2. the capacitor should be placed as close as possible to the package. see "4. errata and design migration guidelines (revision c only)" on page 22 for more details. 3.3.2. output pin termination the nominal output impedance of an isolat or driver channel is approximately 85 : , 40%, which is a combination of the value of the on-chip series term ination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appr opriately terminated with controlled impedance pcb traces. iec specified creepage distance
si8410/20/21 rev. 1.2 21 3.3.3. rf radiated emissions the si841x and si84 2x families use an rf carrier frequency of a pproximately 700 mhz. this results in a small amount of radiated emissions at this frequency and its harmonics. the radiation is not from the ic but, rather, is due to a small amount of rf energy driving the isolat ed ground planes, which can act as a dipole antenna. the unshielded si8410 evaluation boar d passes fcc class b (part 15) requirements. table 13 shows measured emissions compared to fcc requirements. note that the da ta reflects worst-case conditions where all inputs are tied to logic 1 and the rf transmitters are fully active. radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the pcb is a less efficient antenna. 3.3.4. rf, magnetic, and common mode transient immunity the si84xx families have very high common mode transient immunity while transmitting data. this is typically measured by applying a square pulse with very fast rise/fall times between the isolated grounds. measurements show no failures at 25 kv/s (typical). during a high surg e event, the output may glitch low for up to 20?30 ns, but the output corrects immediately after the surge event. the si84xx families pass the industrial requirements of cispr24 for rf immu nity of 10 v/m using an unshielded evaluation board. as shown in figure 13, the isolated ground planes form a parasitic dipole antenna. the pcb should be laid-out to not act as an ef ficient antenna for the rf frequency of interest. rf susceptibility is also significantly reduced when the end system is hous ed in a metal enclosure, or otherwise shielded. the si841x digital isolator can be us ed in close proximity to large moto rs and various other magnetic-field producing equipment. in theory, data transmission errors can occur if the magnetic field is too large and the field is too close to the isolator. however, in actual use, the si84xx devices provide extremely high immunity to external magnetic fields and have been indepe ndently evaluated to withstand magn etic fields of at least 1000 a/m according to the iec 61000-4-8 and iec 61000-4-9 specifications. figure 13. dipole antenna table 13. radiated emissions frequency (mhz) measured (dbv/m) fcc spec (dbv/m) compared to spec (db) 712 29 37 ?8 1424 39 54 ?15 2136 42 54 ?12 2848 43 54 ?11 4272 44 54 ?10 4984 44 54 ?10 5696 44 54 ?10 isolator gnd1 gnd2 dipole antenna
si8410/20/21 22 rev. 1.2 4. errata and design migration guidelines (revision c only) the following errata apply to revision c devices only. see "6. ordering guide" on page 24 for more details. no errata exist for revision d devices. 4.1. power supply bypass ca pacitors (revision c only) when using the isopro isolators with power supplies > 4.5 v, sufficient vdd bypass capacitors must be present on both the vdd1 and vdd2 pins to ensure the vdd rise time is less than 0.5 v/s (which is > 9 s for a > 4.5 v supply). although rise time is power supply dependent, > 1 f capacitors are required on both power supply pins (vdd1, vdd2) of the isolator device. 4.1.1. resolution this issue has been corrected with re vision d of the device. refer to ?6. ordering guide? for current ordering information. 4.2. latch up imm unity (revision c only) isopro latch up immunity generally exceeds 200 ma per pin. exceptions: certain pins provide < 100 ma of latch- up immunity. to increase latch-up immunity on these pins, 100 ? of equivalent resistance must be included in series with all of the pins listed in table 14. the 100 ? equivalent resistance can be comprised of the source driver's output resistance and a series termination resi stor. the si8410 is not affected by the latch up immunity issue described above. 4.2.1. resolution this issue has been corrected with re vision d of the device. refer to ?6. ordering guide? for current ordering information. table 14. affected ordering part numbers (revision c only) affected ordering part numbers* device revision pin# name pin type si8420sv-c-is, si8421sv-c-is c 3 a2 input or output 7 b1 output *note: "sv" = speed grade/isolation rating (aa, ab, ba, bb).
si8410/20/21 rev. 1.2 23 5. pin descriptions name soic-8 pin# si8410 soic-8 pin# si8420/21 type description v dd1 1,3 1 supply side 1 power supply. gnd1 4 4 ground side 1 ground. a1 2 2 digital i/o side 1 digital input or output. a2 na 3 digital i/o side 1 digital input or output. b1 6 7 digital i/o side 2 digital input or output. b2 na 6 digital i/o side 2 digital input or output. v dd2 8 8 supply side 2 power supply. gnd2 5,7 5 ground side 2 ground. narrow body soic v dd1 a1 gnd1 1 2 3 4 5 6 7 8 top view v dd2 b1 gnd2 a2 b2 v dd1 a1 gnd1 1 2 3 4 5 6 7 8 top view v dd2 gnd2 b1 gnd2 v dd1 si841x si842x
si8410/20/21 24 rev. 1.2 6. ordering guide revision d devices are recommended for all new designs. figure 14. ordering part number (opn) convention table 15. ordering guide for valid opns 1 ordering part number (opn) number of inputs vdd1 side number of inputs vdd2 side maximum data rate (mbps) isolation rating temp range package type si8410ab-d-is 1 0 1 2.5 kvrms ?40 to 125 c nb soic-8 si8410bb-d-is 1 0 150 si8420ab-d-is 2 0 1 si8420bb-d-is 2 0 150 si8421ab-d-is 1 1 1 si8421bb-d-is 1 1 150 revision c devices 2 si8410ab-c-is 2 101 2.5 kvrms ?40 to 125 c nb soic-8 si8410bb-c-is 2 1 0 150 si8420ab-c-is 2 201 si8420bb-c-is 2 2 0 150 SI8421AB-C-IS 2 111 si8421bb-c-is 2 1 1 150 notes: 1. all packages are rohs-compliant. moisture sensitivity le vel is msl2a with peak reflow temperature of 260 c according to the jedec industry standard classifications and peak solder temperature. 2. revision c devices are supported for existing designs, but revision d is recommended for all new designs. si84xysv-r-tpn isolator product data channel count reverse channel count max data rate (a=1mbps,b=150mbps) insulation rating (a=1kv, b=2.5kv) product revision temp range (i=-40 to +125c) package type (s=soic) package extension (1=narrow body- 16 pin)
si8410/20/21 rev. 1.2 25 7. package outline: 8-pin narrow body soic figure 15 illustrates the package details for the si841x. table 16 lists the val ues for the dimensions shown in the illustration. figure 15. 8-pin small outline integrated circuit (soic) package table 16. package diagram dimensions symbol millimeters min max a 1.35 1.75 a1 0.10 0.25 a2 1.40 ref 1.55 ref b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e 1.27 bsc h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 ? 0 ? 8 ? ?
si8410/20/21 26 rev. 1.2 8. landing pattern: 8-pin narrow body soic figure 16 illustrates the re commended landing pattern de tails for the si841x in an 8-pin narrow-body soic. table 17 lists the values for the dimensions shown in the illustration. figure 16. pcb landing pattern: 8-pin narrow body soic table 17. pcm landing pattern dimensions (8-pin narrow body soic) dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x173-8n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si8410/20/21 rev. 1.2 27 9. top marking figure 17. isolator top marking table 18. top marking explanations line 1 marking: base part number ordering options (see ordering guide for more information). si84 = isolator product series xy = channel configuration x = # of data channels (2, 1) y = # of reverse channels (1, 0) s = speed grade a = 1 mbps; b = 150 mbps v = insulation rating a = 1 kv; b = 2.5 kv line 2 marking: yy = year ww = workweek assigned by assembly contractor. corresponds to the year and workweek of the mold date. r = product (opn) revision f = wafer fab line 3 marking: circle = 1.1 mm diameter left-justified ?e3? pb-free symbol first two characters of the manufacturing code a = assembly site i = internal code xx = serial lot number last four characters of the manufacturing code si84xysv yywwrf aixx e3
si8410/20/21 28 rev. 1.2 d ocument c hange l ist revision 0.11 to revision 0.21 ? rev 0.21 is the first revision of this document that applies to the new series of ultra low power isolators featuring pinout and func tional compatibility with previous isolator products. ? updated ?1. electrical specifications?. ? updated ?6. ordering guide?. ? added ?9. top marking?. revision 0.21 to revision 0.22 ? updated all specs to re flect latest silicon. revision 0.22 to revision 0.23 ? updated all specs to re flect latest silicon. ? added "4. errata and design migration guidelines (revision c only)" on page 22. revision 0.23 to revision 1.0 ? updated document to reflec t availability of revision d silicon. ? updated tables 1,2, and 3. ?? updated all supply currents and channel-channel skew. ? updated table 4. ?? updated absolute maximum supply voltage. ? updated table 7. ?? updated clearance and creepage dimensions. ? updated "4. errata and design migration guidelines (revision c only)" on page 22. ? updated "6. ordering guide" on page 24. revision 1.0 to revision 1.1 ? updated tables 1, 2, and 3. ?? updated notes in tables to reflect output impedance of 85 : . ?? updated rise and fall time specifications. ?? updated cmti value. revision 1.1 to revision 1.2 ? updated document throughout to include msl improvements to msl2a. ? updated "6. ordering guide" on page 24. ?? updated note 1 in ordering guide table to reflect improvement and compliance to msl2a moisture sensitivity level.
si8410/20/21 rev. 1.2 29 n otes :
si8410/20/21 30 rev. 1.2 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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